1. Field of the Invention
This invention relates to Class-D amplifier circuits with offset compensation or correction, especially to Pulse-Density-Modulated, Sigma-Delta or Pulse Width Modulated Class-D amplifiers with a full H-bridge or half-bridge output stage.
2. Description of the Related Art
FIG. 1 shows a basic arrangement of one example of a pulse-density-modulated (PDM) Class-D amplifier, sometimes referred to as a Sigma-Delta amplifier. An output stage 101 comprises four switches connected in a full H-bridge arrangement between two supplies, typically a supply voltage Vdd and ground (GND). Feedback signals from the output terminals 102 and 103 of the H-bridge 101 are respectively subtracted from the input signals Vin+ and Vin− of the amplifier in order to generate an error signal which is passed through a loop filter 104, for example an integrator.
The output signal from the loop filter 104 is quantized by a comparator 105 that is clocked to provide a digital control signal at a desired drive frequency FDD. The desired drive frequency FDD is significantly higher than the frequency of the input signals to be amplified, Vin+ and Vin−, and, for an audio amplifier, the desired drive frequency FDD may have a frequency of the order of MHz, for example 3 MHz.
The digital control signal from the comparator 105 may be passed through optional logic 106 before being received by the pre-driver logic 107 to generate buffered gate drive signals for controlling the switches in the H-bridge output stage 101.
In a basic Class-D amplifier such as illustrated in FIG. 1 the H-bridge output may be operable in two states only, those illustrated as states A and B in FIG. 2: it should be noted that in use a load is connected between the output terminals 102 and 103 of the H-bridge 101. In continuous state A, assuming the upper rail is at Vdd and the lower rail is at ground, the output voltage across the load, i.e. terminals 102, 103, will settle to +Vdd (ignoring any switch voltage drops). In continuous state B, the voltage across the load will settle to −Vdd. Switching between states A and B with an effective duty of cycle of 50:50 will result in an output that averages to zero volts, and other duty cycles will result in intermediate differential average output voltages. Thus the switch drive signals from the pre-driver logic 107 control the H-bridge output to switch between states A and B as required and the output is averaged by an inductance (possibly an inductance associated with the load) to give low (e.g. audio) frequency components which follow the input signal.
Class-D amplifiers in which the H-bridge output 101 is operable in three states are also known. In such an amplifier the H-bridge output 101 may be operated in a third state, state C as illustrated in FIG. 2, in which both output terminals 102, 103 are connected, i.e. switched, to ground. The comparator 105 of FIG. 1 may therefore be modified to generate three output logic states, which may be regarded as +1, 0, −1 say, by comparing the integrated error signal at the output of the loop filter 104 against two separate thresholds, for example +Vdd/3 and −Vdd/3. The logic states +1, 0, −1 drive the H-bridge stage 101 in states A, C, B respectively. The use of state C, which has a differential output of zero, can reduce the number of transitions between states at low signal levels, thus saving on power and reducing ripple on the output which could otherwise lead to unwanted EMI.
In some amplifiers the H-bridge stage 101 may additionally be operated in a fourth state, state D in FIG. 2. In this fourth state both output terminals 102, 103 are connected, i.e. switched, to Vdd. This state D, like state C, thus has a differential output of zero. Logic circuitry 106 is typically arranged to ensure that, in those cycles where a zero differential voltage is desired, i.e. the output of the logic circuitry 106 is a logic 0, each of states C and D is chosen on average for half of those cycles. The inclusion of state D can avoid any signal dependent modulation of the common-mode output voltage and any associated distortion thus saving on power and reducing ripple on the output which could otherwise lead to unwanted EMI.
The embodiment shown in FIG. 1 is an example of a Pulse-density-modulated (PDM) Class-D amplifier. Pulse-width-modulation (PWM) control is also known where the output stage is switched between states A and B, and possibly states C and optionally D, by pulses of varying widths possibly based on comparing the input signal (or an error signal derived therefrom) to a time-varying cyclic reference signal. Examples of time-varying cyclic reference signals comprise, for example, a zigzag type wave such as a triangle wave or sawtooth wave, a square wave or a sinusoidal wave.
DC offset can be a problem in Class-D amplifiers such as described above, especially when used for audio applications. For the H-bridge output stage described above, the peak differential voltage across the load will either be +Vdd or −Vdd, so it is natural for the quiescent output voltage across the load to be set to zero, and as a result this requires no AC coupling/DC blocking capacitor. Similarly for the case of a half-bridge output stage driving a grounded load from symmetrical bipolar supplies say +Vdd and −Vdd, the notional quiescent output voltage is ground and likewise no AC coupling/DC blocking capacitor would be required for the output signal. The presence of a DC offset voltage at the output of the audio amplifier can lead to an offset voltage being suddenly imposed on the speaker load at power-up, or conversely suddenly removed at power-down, which may lead to an audio artefact such as an audible ‘pop’. Such an audio artefact is undesirable and should be reduced, or preferably avoided, if possible. Further, in the absence of any DC blocking capacitor the presence of a DC offset voltage at the output of an amplifier can lead to power wastage due to the resultant quiescent load current. Such wastage is an issue for battery powered devices such as mobile phones for example where unnecessary power consumption reduces battery life.
Embodiments of the present invention therefore provide methods and apparatus for Class-D type amplification that at least mitigate some of the above mentioned disadvantages.